Data has conventionally been stored in random access memories (RAMs) like dynamic RAMs (DRAMs) in an uncompressed format. With the increasing cost of memory, and the increasing reliance of computing systems on DRAMs, efforts to conserve space in memory have occurred. These efforts have typically been concerned with compressing data in main memory. When data has been stored in a compressed format in main memory, the goal has generally been to save space. However, saving space in a DRAM may lead to a given block of data having no specific location pre-allocated in the DRAM, which may slow data transfers. Thus, storing a block of data in a compressed format may require compressing it, determining its size, and finding a free area of memory that can hold the compressed block. These conventional actions may entail performing complicated and thus time-consuming methods for determining true DRAM row and column data addresses. Also, these methods are typically performed after the data has been compressed. Thus, these conventional schemes, while saving memory space may negatively impact memory transfer bandwidth.
DRAMS are typically packaged in dual in-line memory modules (DIMMs). A DRAM may have millions of memory locations called cells. Each cell stores one bit of information. The cells are typically arranged in a matrix of rows and columns. A DRAM row may be referred to as a page. To access a DRAM cell, a memory controller sends electronic signals specifying the row address and column address of the target cell. The memory controller sends these row/column signals via a memory bus or memory interface that may have both address/command lines and data lines. The data lines carry data between a memory controller and a DRAM while the address/command lines carry addresses and commands between the memory controller and the DRAM. The data throughput between the memory controller and the DRAM depends on the number of data lines available (e.g., 64), and the frequency at which data can be transferred over those data lines.
Accessing a cell typically includes identifying to a DRAM a row in which the cell is located and then identifying to the DRAM a column in which the cell is located. Identifying the row typically includes a row address selection (RAS) action. Similarly, identifying the column typically includes a column address selection (CAS) action. Thus, in some systems, acquiring each bit of data may require two address/command actions. Therefore, some original DRAMS required multiple (e.g., up to six) system bus cycles for each memory access. This may lead to bottlenecks when transferring data to and/or from memory.
Additionally, when data is transferred from a processor to a memory controller and then to a memory, a bandwidth disparity may exist if the bandwidth of the processor to memory controller connection (e.g., front side bus) is greater than the bandwidth of the memory controller to memory connection (e.g., memory interface). This bandwidth disparity may also lead to bottlenecks when transferring data to and/or from memory. This bottleneck may be exacerbated by conventional memory-controller based (de)compression apparatus if a (de)compression latency exceeds a read/write latency. Since space-saving is the focus of these conventional systems, design trade-offs have typically accepted the bottleneck to achieve space savings.
To address at least part of these bottleneck issues, a burst-mode protocol has been employed for interacting with DRAMs. In one example burst-mode protocol, a single RAS action, followed by a single CAS action may lead to two or more bits of data being transferred to and/or from a DRAM. For example, a single RAS/CAS pair may cause four sequential data locations to be transferred. The most efficient data transfers would occur if a single RAS/CAS pair could be employed to transfer an entire row to and/or from a DRAM.
As is conventionally practiced, data that reside all within one row of a DRAM require only one new address command to be sent. Typically DRAM controllers take advantage of this and may also take advantage of burst-mode protocols. Furthermore, memory subsystems may set up DRAM mappings so that entire cache lines or typical data block structures start on appropriate burst-mode boundaries and do not cross new address (page) boundaries. However, typical compression schemes that focus on saving space leave a memory controller to track both size and starting location for a given data block.
Cache lines have sizes that are typically a multiple of burst-mode boundaries and a sub-multiple of a row boundary. Thus, cache lines typically have known starting points that facilitate uncompressed data from requiring less than an integer multiple of burst cycles or from requiring the data to cross multiple row boundaries.